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austriamicrosystems ag is now ams ag the technical content of this austriamicrosystems datasheet is still valid. contact information: headquarters: ams ag tobelbaderstrasse 30 8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 e - mail: ams_sales @ams.com please visit our website at www.ams.com
preliminary datasheet as3510 rev. 1v2, june 2004 confidential page 1 of 19 general description the as3510 combines high flexibility and outstanding performance for analog audio front-end solutions. this codec-chip contains a high performance 18 bit digital to analog converter. the dynamic range exceeds 95db for best audio quality, for multi media applications (audio playback) within battery or line operated equipment. an additional audio power amplifier can directly drive external headphones or small 4 ? speakers with a power of up to half a watt. the power-up is click- and pop-less due to a smooth start-up circuitry. the overall distortion level is always below 0.02%. the microphone input amplifier contains an automatic gain control (agc) with a dynamic range of 40db to generate an amplified and compressed signal for the adc, which provides 14 bit resolution at 8khz sampling-rate. furthermore all necessary power management is included such as bandgap reference and four voltage regulators. the two 2.9v regulators are used internally (analog and digital supply), but can also be used for external purposes as well. the third output is designed to supply the peripheral cells and an external digital core, and is programmable from 1.5v to 2.5v in 5 steps (default is 2.5v). they are all powered through a dcdc-converter, which can work down to a voltage of 1v. so the whole chip can work from a single battery cell. the fourth regulator is only used for generating the supply voltage for the analog usb 1.1 interface circuit. it is supplied via the usb connector. the performance of the regulators is excellent (noise, line- and load-regulation) and allows the direct supply of sensitive analog circuits. because of the internal supply and signal filtering only few small external capacitors are required for de-coupling and stabilising and lead to very low output noise. the current consumption is very low and makes the chip ideally for battery powered devices. key features on chip dcdc converter - 1.0 to 5.5v input voltage range 4 on-chip high performance voltage regulators - digital supply, 2.9v - analog supply, 2.9v - core supply, 1.5 to 2.5v - usb transceiver supply, 3.2v 18 bit stereo dac - dynamic range >95 db - thd < -85db - de-emphasis for 32 khz, 44.1 khz and 48 khz stereo power audio amplifier - max. 2x 0.5w @ 4 ? - analog volume control ?39db to +3db, 3db steps including mute) - click- and pop-less startup and power down - auxiliary inputs for additional audio sources microphone input - 14 bit ?? adc , 8khz sampling rate - automatic gain control (agc) - low power consumption - wide battery supply range 1.0v ? 5.5v - standard i2s interface - audio sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, and 48 khz - i2c control interface - usb 1.1 front-end - 49 pin bga package applications - audio frontend for cellular phones - stand alone mp3 player - cd and dvd player - pdas analog voice codec as14889 preliminary data sheet analog audio front-end as3510 data sheet confidential ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 2 of 19 block diagram ldo1 right gain control +3...-39db power amplifier serial audio interface (i2s) & clock generation interpolator *64 interpolator *64 multibit sd modulator with dwa multibit sd modulator with dwa dac + sc lpf dac + sc lpf bgnd buffer pop-less startup -outr -bvss -outl -bgnd - qldo3 -qldo2 - qldo1 - avdd referenze voltage & current generation - avss2 - avss - vref - agnd - micn - micp ldo3 ldo2 amplifier gain control +3...-39db left power dvss - microphon amplifier 2nd order sd adc 14bit, 8khz + interpolator digital i2s synchronisation dither generation head- phone jack v_reg1 v_reg3 v_reg2 100n 10u 100n 10u 2,2u / 6,3v z5u 2,2u / 6,3v z5u 2,2u / 6,3v z5u c2,2u with rl=150 ohm, or 330u with rl=8 ohm 2,2u with r l =150 ohm, or 330u with r l =8 ohm 1 to 5.5v 2,9v, 50ma @ bvdd=3v 2,9v, 50ma @ bvdd=3v enldo12 - pldo3 - endcdc - control interface (i2c slave) scl sda dcdc converter usb 1.1 + ldo3.2v auxr - auxl - x x x x single ended to differental converter uvdd - vtrm - d- - d+ - - - vbat1v - - sw vss - bvdd - - pvdd - dvdd -bvdd sdo - mclk - lrck - sclk - sdi - p digital audio interface p control interface vtrm bvdd avss bvdd avss bvdd avss bvss bvdd bvdd bvss bvdd bvss vpo - vmo - vp - vm - oen - rcv - usb connector p usb interface battery 1,75v to 2.5v, 200ma @ bvdd=3v figure 1 block diagram of as3510 ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 3 of 19 modes of operation inputs outputs ldo-modes enldo12 enldo3 dvdd, avdd pvdd off ll ldo1, ldo2 are off 2.8?3.6v supply fr. ext. ldo3 is off 1.75-3.6v supply fr. ext. on_12 hl ldo1, ldo2 are on output is 2.9vtyp ldo3 is off 1.75-3.6v supply fr. ext. or connected to dvdd on_123 hh ldo1, ldo2 are on output is 2.9vtyp ldo3 is on output 2.5vtyp table 1 ldo operating modes nodes: - 1. bvdd as input to the ldo regulators has to be >=3.0v. - 2. dvdd - avdd max. difference of 100mv. - 3. pvdd has to be lower or equal to dvdd. - 4. ldo1 is to be used for regulating avdd (connect pin 25 to pin 26) - 5. ldo2 output is internaly connected to dvdd (pos. digital supply) - 6. ldo3 output is internaly connected to pvdd (pos. peripheral supply) inputs outputs dac-modes dacpd i2s gain3:0 outr, outl off h x llll tristate dac_on l lrck up to 50khz mclk ? 128*f(lrck) sclk l=>h strobes sdi sclk ? >=38*f(lrck) sdi left justified with msb first at 2 nd sclk edge llll tristate audio_on l lrck up to 50khz mclk ? 128*f(lrck) sclk l=>h strobes sdi sclk ? >=38*f(lrck) sdi left justified with msb first at 2 nd sclk edge lllh . . hhhh stereo audio output with poweramp gain adjusted in 3db steps by gain(3:0) table 2 dac operating modes nodes: - during supply voltages settling at system start-up gain(3:0) should be held ?l?. - the mclk frequency ratio to lrck is permanently checked. if the ratio is different to 128, the dac goes in reset-mode (no audio will betransferred). - mclk rising edge should not be within +/-10ns of lrck edges. - capacitors at vref, agnd and bgnd are needed for the dac operation. - the sclk has to have at least 34 or 38 cycles within one lrck cycle 2*(16bit data + the leading empty bit) or 2*(18bit data + the leading empty bit) - there can be more sdi bits presented but just the first 18 bits are transferred. ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 4 of 19 inputs output adc-modes enadc i2s-clocks lrck, sclk,mclk micp/micn sdo off l x x static l adc_on h lrck up to 50khz mclk ? 128*f(lrck) sclk ? >=34*f(lrck) differential analog input to be converted to digital output sdi serial data output ieft justified to lrck with msb first at 2 nd sclk edge table 3 adc operating modes nodes: - there are 16bit presented at sdo at each cycle but just the first 14 do have relevalt data. - the adc is a single channel (mono) path. the same sdo bitstream is presented for left and right channel of one cycle. - the adc sampling rate is equal to lrck/4. this means that the sdo bitstream gets updated at each 4 th cycle of lrck. - sclk has to have at least 34 cycles within one lrck cycle 2*(16bit data + the leading empty bit) ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 5 of 19 functional description audio dac block description this block is the complete audio dac delivering 93db dynamic range. it is comprised of a multibit sigma-delta modulator with dither option and a switched-capacitor analog filter. this architecture provides a high insensitivity to clock jitter. a digital interpolation filter increases the sample rate by a factor of 8 using 3 linear phase, half-band filters cascaded, followed by a first order sinc interpolator with a factor of 8. this filter eliminates the images of baseband audio remaining only the image at 64* the input sample rate. optionally, a dither signal can be added that may reduce eventual noise tones at the output. however, the use of a multibit delta-sigma modulator already provides extremely low noise tone energy. signal description setting dacpd to 1 forces the analog section to power- down. for normal-operation the i2s signals have to be applied as shown below: 15 0 17 2 01 15 0 17 2 01 mclk lrck sclk sdata(16) sdata(18) 64 mclk cycles left channel 64 mclk cycles right channel figure 2 i2s waveforms the lrck defines if the transferred data is for the left or right channel (l=left). with the rising edge of the serial clock sclk , the inputdata gets strobed. the data word at sdata is max. 18 bit with msb first and 2 nd complement coded. all i2s signals change state with falling edge of sclk. code hex value max. positive code 1ffff (hex) +1 00001 (hex) 0 00000 (hex) -1 3ffff (hex) max. negative code: 20000 (hex) table 4 i2s code values if the dataword length is less than 18 bit, zeros have to be added to avoid any offset value. the frequency of master clock mclk has to be 128 times the input sample rate (f(lrck)*128) with low jitter. the rising edge of mclk should be separated by >10ns from lrck edges. there are 2 pins needed for the generation and decoupling of reference-voltages for the dac. agnd is avdd/2 and vref is equal to avdd. both pins have high output resistance which provides a suitable lowpass filter for these reference voltages with external capacitors of 10uf in parallel with 100nf. the supply lines are separate for digital dvss / dvdd and analog avss / avdd to minimise coupling influences. the analog output is differential stereo signal at nodes outrn, outrp and outln, outlp respectively. ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 6 of 19 control interface the interface is a standard i2c slave interface (write only). the system uses address group 8 address 41h for audio- processors. the following table shows the various control options. byte 0 (default value: 0x80h) bit name description 7 dith dither enable 1: enable (default) 0: disable 6..5 dacon 11: audio dac is switched on 10: audio dac is switched on 01: audio dac is switched off 00: automatic mode, dac is on only when i2s interface is active 4 lp4/16 audio amplifier load switch 1: low power mode for speakers with more than 16 ohm. 0: normal mode, 4 ohm loads possible 3..0 gain gain settings for audio amplifier from ?39db to +3db in steps of 3db 1111: full output swing: +3db 1110: 0db . 0010: -36db 0001: minimum output swing: -39db 0000: mute table 5 ? software i2c byte 0 byte 1 (default value: 0x10h) bit name description 7 - not used 6 fadc2 1: doubles the sampling adc freq. 0: normal adc sampling frequnecy 5 usbspn 1: normal usb operation 0: suspend usb 4 pwuphld 0: switch off 3 auxen 1: enable aux inputs 0: disable aux inputs 2 adcen 1: adc enable for microphone input 0: adc disable 1..0 micgain gain settings for microphone amplifier 11: 40db 10: 40db 01: 34db 00: 28db table 6 ? software i2c byte 1 the powerup hold (pwuphld; bit 4) is when an high pulse on the powerup pin occures. to switch of the as3520 the pwuphld bit must be cleared. byte 2 (default value: 0x01h) bit name description 7..6 iaudio audio amplifier supply current 11: 50% 10: 66% 01: 83% 00: 100% (default) 5..4 idac audio dac supply current 11: 50% 10: 60% 01: 75% 00: 100% (default) 3..1 - not used, must be set to 000 0 mclk# 1: dac uses inverted mclk 0: dac uses normal mclk table 7 ? software i2c byte 2 byte 3 (default value: 0x11h) bit name description 7..4 version not used 3 - not used 1..2 - not used, must be set to 000 0 i2sdir 1: only 18bit data are accepted 0: also less than 18 bit can be sent to the i2s interface and are shifted internal table 8 ? software i2c byte 3 ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 7 of 19 power amplifier block description the power amplifier block converts the differential output signals from the audiodac into single ended signals with the drive capability for impedances 4 ohms. with the conversion from differential to single ended, the transformation of dc level from agnd (=avdd/2) to bgnd (=bvdd/2) is done. the gain of this driver stage can be set by 4 digital input signals in the range from ?39db to +3db in steps of 3db. with the maximum gain of +3db, full scale gives 4.95vpp at the single ended output. with i2s data giving full-scale swing, clipping will occur with the max. gain-step. with min. bvdd of 3.0v the same is true for the two highest gain-steps. when the control signals gain(3:0) are all set to ?l?, the block is set to power-down. there is a bgnd generation, which needs an external capacitor of 100nf for blocking of low frequency components at bvdd. with this external capacitor, a so called ?klickless on? is performed so that at power-up, the output terminals have a smooth startup to avoid any transient noise in the headphone. gain (3:0) gain dif se fs swing gain (3:0) gain dif se fs swing h h h h +3db 4.95vpp l h h h -21db 309mvpp h h h l 0db 3.50vpp l h h l -24db 219mvpp h h l h -3db 2.47vpp l h l h -27db 155mvpp h h l l -6db 1.75vpp l h l l -30db 109mvpp h l h h -9db 1.24vpp l l h h -33db 77mvpp h l h l -12db 0.87vpp l l h l -36db 55mvpp h l l h -15db 0.62vpp l l l h -39db 39mvpp hlll -18db 0.44vpp llll off - table 9 table of gain steps ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 8 of 19 supply regulator block description this block can be used to provide three regulated supply voltages for the - on_chip digital section - on_chip analog section - external circuit (up, dsp?) from the battery supply bvdd which is directly used by the power_amplifier. the ldo1 and ldo2 do have the capability to drive 50ma with a voltage drop of <=50mv (1ohm). since the nominal output voltage for these ldos is 2.9v (+/-50mv), a regulation can be done with bvdd as low as 3.0v. the ldo3 is used to generate a supply voltage pvdd for the peripheral cells and external digital circuits, which are controlling the inputs of the as3510. the drive capability is 200ma with a bvdd 3v. the maximum output currents for these ldos can be calculated using the following equation: ohm mvvoutbvdd i 1 50 ) (( max +? = vout is 2.9v for ldo1 and ldo2. the output voltage for ldo3 can be programmed via the pldo3 pin. pld3 pin qldo3 voltage vss 2.25v 150k to vss 2.0v open 2.5 150k to dvdd 1.5 dvdd 1.75 table 10 ldo3 programming there are two pads at each ldo, one is the ldo output pad and the second is the corresponding chip supply pad, which are bonded to the same pin (ldo1 only), and have external blocking caps (cblock with low esr). if supply should not be generated from the on_chip ldos, these blocks can be disabled with control pin powerup. avdd, dvdd and pvdd can then be forced from external regulators. ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 9 of 19 microphone path block description this block converts a differential microphone signal into digital and does a synchronisation to the dac i2s input clocks. the sigmadelta converter clock gets derived from mclk. for lrck=32khz mclk=4.096mhz, the sd_clk is 1.024mhz which gives with decimation to 14 bit a sampling rate of 8khz. since the i2s signals for the dac- path is 4 times higher, each adc-output-code will be presented 4 times in both channels (left, right) the same. for lrck=48khz mclk=6.144mhz, the adc conversion rate will be 12khz. due to this synchronisation the transfer of the adc data is possible with just one extra digital output pin which makes the digital interface very efficient. the microphone amplifier can be programmed to three different gain values 28db/ 34db/ 40db to adjust the circuit to the used microphone. the microphone amplifier includes a softclip function that reduces the gain when the input voltage range of the adc is violated. the fullscale adc input range is 1.157vp differential with avdd=2.9v. the softclip references are +/-0.434v which gives a useable adc-range of 0.868vp differential. this gives a nominal mic input voltage range of 34.72 / 17.36 / 8.68mvp or 24 /12 / 6mvrms for the three micamp gain settings. softclip is done with 15 steps of ?1db. ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 10 of 19 specifications electrical characteristics absolute maximum ratings parameter symbol min max unit note dcdc input supply voltage vbat1.0 -0.5 5.0 v battery input supply voltage bvdd -0.5 7.0 v usb input supply voltage uvdd -0.5 7.0 v avdd input supply voltage avdd -0.5 5.0 v pvdd input supply voltage pvdd -0.5 5.0 v dvdd input supply voltage dvdd -0.5 5.0 v voltage between vss-terminals vss_dcdc, bvss, avss, dvss xvss -0.5 0.5 v voltage at pins: powerup, pldo3, micp, micn, vref, agnd, bgnd, qldo3, qldo2, sw vin -0.5 avdd+0.5 v voltage at pins: cscl, csda vin -0.5 5.0 v no diode to dvdd voltage at pins: auxl, auxr, outl, outr vin -0.5 bvdd+0.5 v voltage at pins: vtrem, dp, dm vin -0.5 5.0 v all other digital input pins v i -0.5 dvdd+0.5 v input current (latchup immunity) iscr -100 100 ma electrostatic discharge 1 kv hbm, iec61000-4-2 storage temperature tstrg -55 125 o c soldering conditions t lead 240 o c iec61760-1 humidity non-condensing 5 85 % table 11 table of absolute maximum ratings operating conditions parameter symbol min typ max unit analog input supply voltage avdd 2.8 2.9 3.6 v digital input supply voltage dvdd 2.8 2.9 3.6 v digital core input supply voltage pvdd 1.5 2.5 v battery input supply voltage bvdd 3.0 3.2 5.5 v dcdc input supply voltage vbat1.0 1.0 1.5 3.6 v usb input supply voltage uvdd 4.0 5.0 5.5 v ambient temperature -20 25 85 c table 12 table of operating conditions ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 11 of 19 block characteristics overal l supply min typ max unit avdd (avdd = 2.9 v) 2.6 9 ma dvdd analog (dvdd = 2.9v) 4.5 8.5 ma idd in power down < 1 10 ua table 13 table of overall block characteristics audiodac parameter min typ max unit analog performance thd+noise at ?1db_fs -85 -75 db dynamic range (20hz-20khz, -60dbfs) 90 93 db interchannel mismatch 0.25 db table 14 table of audiodac block characteristics power amplifier parameter min typ max unit analog performance r_load at aoutr and aoutl differential 8 ohm r_load at aoutr and aoutl single ended 4 ohm gain step precision (rlmin-max,20hz-20khz) 0.5 db thd @ 1khz, bvdd=3-5v, gain=8, no load - - 0.03% % psrr (200hz-20khz) 60 - - db iout_powerdown -20 20 ua tpower_up (cbgnd=100nf) 200 ms table 15 table of power amplifier block characteristics ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 12 of 19 supply regulator parameter min typ max unit por performance dvdd_por_off - 2.15 v dvdd_por_on 2.0 - v por_on/off_hyst 100 mv lrck watchdog with dvdd=2.9v f(lrck)_wd_off - 4.1 khz f(lrck)_wd_on 3.91 - khz on_delay 50 us table 16 table of supply regulator block characteristics microphone path parameter min typ max unit analog performance rinp_dif (micp, micn) 30 kohm gain_micamp_0 28 db gain_micamp_1 34 db gain_micamp_2 40 db softclip_agc_range 15*1.0 db attack_time 39 us/st release_time 80 ms/st mic vin full scale_0 (avdd=2.9v) 24 mvrms mic vin full scale_1 (avdd=2.9v) 12 mvrms mic vin full scale_2 (avdd=2.9v) 6 mvrms decimation rate 128 enob 14 bit snr 71 db psrr tbd db table 17 table of microphone path block characteristics ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 13 of 19 measurements the following measurement curves are the results from noise measurements on the as3510 dac. ta.: 25c, vdd: 2.9v, signal: 1khz, 0db fs , clk:128*48khz figure 3 sinad measurement at 0dbfs ta.: 25c, vdd: 2.9v, signal: 1khz, -20db fs , clk:128*48khz figure 4 sinad measurement at -20dbfs ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 14 of 19 package and pinning pin configuration for tqfp80 pin# pinname type function 25 dvss supply neg. supply of digital circuit 27 pvdd supply supply of peripheral levelshifter of digital inputs 28 dvdd supply pos. supply of digital circuits 29 mclk din with pull down master clock 128*fs / left open - enables pll 31 lrck din with pull down i2s_left/right frameclock = fs 32 sclk din with pull down i2s_serial data clock >=38*fs 33 sdi din with pull down i2s_serial data 18bit left oriented, first bit fix l 36 cscl din stt + spike supr i2ccomp_serial clock to access control register 37 csda di/od stt + spike supr i2ccomp_serial data to access control register 38 sdo dout_2ma i2s_serial data 14bit left orieted, first bit fix l 39 usbon dout_2ma usb_indication of usb supply present 40 rcv dout_2ma usb_differential receiver output 41 vp dout_2ma usb_signle ended pos. receiver output 42 vm dout_2ma usb_signle ended neg. receiver output 43 vpo din with pull down usb_transmitter pos. input 44 vmo din with pull down usb_transmitter neg. input 45 oen din with pull up usb_transmitter output enable (low active) 46 dvss supply neg. supply of digital circuit 47 dp di/o with 1ua pd usb_pos. i/o terminal 48 dm di/o with 1ua pd usb_neg. i/o terminal 49 vtrm aout/supply usb_3.2v termination voltage regulator output 50 uvdd supply usb_external supply 4-5.5v 51 aux_r ain 40/200k to bgnd analog aux input to audio amp right channel 52 aux_l ain 40/200k to bgnd analog aux input to audio amp left channel 53 pwrup din 360k pull down enable ldo1 and 2 and dcdc 54 pldo3 din_5state selects one of 5 ldo3 states (l, 150kpd open, 150kpu, h) 55 micp ain 15k to agnd microphone pos. input (mic-adc path) 56 micn ain 15k to agnd microphone neg. input (mic-adc path) 57 vref ai/o 10uf decpl reference voltage of dac (avdd) 58 agnd ai/o 10uf decpl reference voltage of dac (avdd/2) 59 avss supply neg. supply terminal of analog circuit 60 avss2 supply 2 nd neg. supply terminal of analog circuit 64 avdd aout/supply pos. supply of analog circuits, ldo1 output ? 2.9v 65 bgnd ai/o 100nf decp reference voltage of power-amp (bvdd/2) 66 bvdd supply battery supply 3-5.5v 67 outr aout speaker/headphone output (4 ohm min.) 68 bvss supply neg. supply terminal of power amp. 69 outl aout speaker/headphone output (4 ohm min.) 70 bvdd supply battery supply 3-5.5v 71 qldo2 aout ldo2 output ? 2.9v to be connected to dvdd 72 qldo3 aout ldo3 output ? 1.5?2.5v to be connected to pvdd 73 vssdcdc supply power ground for dcdc converter 74 vssdcdc supply power ground for dcdc converter 75 swdcdc aout switch output for dcdc converter 76 swdcdc aout switch output for dcdc converter 77 vb1v supply battery supply input (1v-3v) table 18 table of pin configuration for tqfp80 ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 15 of 19 pin configuration for cabga 49 ball# ballname type function f1 dvss supply neg. supply of digital circuit b2 pvdd supply supply of peripheral levelshifter of digital inputs a2 dvdd supply pos. supply of digital circuits g1 mclk din with pull down master clock 128*fs / left open - enables pll d2 lrck din with pull down i2s_left/right frameclock = fs e2 sclk din with pull down i2s_serial data clock >=38*fs f2 sdi din with pull down i2s_serial data 18bit left oriented, first bit fix l g2 cscl din stt + spike supr i2ccomp_serial clock to access control register g3 csda di/od stt + spike supr i2ccomp_serial data to access control register f3 sdo dout_2ma i2s_serial data 14bit left orieted, first bit fix l e3 usbon dout_2ma usb_indication of usb supply present g4 rcv dout_2ma usb_differential receiver output f4 vp dout_2ma usb_signle ended pos. receiver output e4 vm dout_2ma usb_signle ended neg. receiver output e5 vpo din with pull down usb_transmitter pos. input f5 vmo din with pull down usb_transmitter neg. input d5 oen din with pull up usb_transmitter output enable (low active) g5 dvss supply neg. supply of digital circuit g6 dp di/o with 1ua pd usb_pos. i/o terminal g7 dm di/o with 1ua pd usb_neg. i/o terminal f6 vtrm aout/supply usb_3.2v termination voltage regulator output f7 uvdd supply usb_external supply 4-5.5v d7 aux_r ain 40/200k to bgnd analog aux input to audio amp right channel d6 aux_l ain 40/200k to bgnd analog aux input to audio amp left channel e7 pwrup din 360k pull down enable ldo1 and 2 and dcdc e6 pldo3 din_5state selects one of 5 ldo3 states (l, 150kpd open, 150kpu, h) c7 micp ain 15k to agnd microphone pos. input (mic-adc path) c6 micn ain 15k to agnd microphone neg. input (mic-adc path) c5 vref ai/o 10uf decpl reference voltage of dac (avdd) b6 agnd ai/o 10uf decpl reference voltage of dac (avdd/2) b7 avss supply neg. supply terminal of analog circuit a7 avdd aout/supply pos. supply of analog circuits, ldo1 output ? 2.9v a6 bgnd ai/o 100nf decp reference voltage of power-amp (bvdd/2) b5 bvdd supply battery supply 3-5.5v a5 outr aout speaker/headphone output (4 ohm min.) a4, b4 bvss supply neg. supply terminal of power amp. a3 outl aout speaker/headphone output (4 ohm min.) b3 bvdd supply battery supply 3-5.5v a1 vssdcdc supply power ground for dcdc converter b1 vssdcdc supply power ground for dcdc converter c1 swdcdc aout switch output for dcdc converter d1 swdcdc aout switch output for dcdc converter e1 vb1v supply battery supply input (1v-3v) c2 n.c. not connected c3 n.c. not connected c4 n.c. not connected d4 n.c. not connected table 19 table of pin configuration for cabga 49 ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 16 of 19 vssdcdc dvdd outl bvss vssdcdc pvdd bvdd bvss outr bgnd bvdd agnd 1234567 a b c d e f g avdd avss swdcdc n.c. ( qpll ) n.c. ( reset ) n.c. swdcdc lrclk dacpd n.c. vref micn oen auxl micp auxr vb1v sclk usb_on vm dvsds sdi sdo vp vpo pldo3 vmo vtrm pwrup uvdd mclk cscl csda rcv dvss dp dm figure 5 figure of pin configuration mechanical dimensions for cabga 49 figure 6 mechanical dimensions ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 17 of 19 abbreviations adc analog to digital converter agc automatic gain control dac digital to analog converter dbfs db full scale dsp digital signalling processor enob effective number of bits esd electrostatic discharge i2s inter ic sound ldo low drop regulator pda personal digital assistance psrr power supply rejection ratio sfdr spurious free dynamic range sd sigma delta snr signal to noise ratio sinad signal to noise and distortion (=thd+n) ta ambient temperature thd total harmonic distortion up microprocessor ? sigma delta ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 18 of 19 ordering information number package description as3510 lqfp 80 thin quad flat pack - 80 leads (evaluation only) cabga 49 chiparray ball grid array ? 49 balls, 0.8mm pitch devices sold by austriamicrosystems ag are covered by the warranty and patent identification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. copyright copyright ? 2004, austriamicrosystems ag, schloss premstaetten, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. ams ag technical content still valid
product brief as3510 rev. 1v2, june 2004 confidential page 19 of 19 contact headquarter austriamicrosystems ag business unit communications a 8141 schloss premst?tten, austria t. +43 (0) 3136 5440 f. +43 (0) 3136 5692 accento@austriamicrosystems.com www.austriamicrosystems.com sales offices austriamicrosystems germany gmbh tegernseer landstrasse 85 d-81539 mnchen, germany phone: +49/89/693643-0 fax: +49/89/693643-66 austriamicrosystems france s.a.r.l. 124, avenue de paris f-94300 vincennes, france phone: +33/1/43 74 00 90 fax: +33/1/43 74 20 98 austriamicrosystems italy s.r.l. via leone tolstoi, 64 i-20146 milano, italy phone: +39/0242/36713 fax: +39/0242/290889 austriamicrosystems switzerland ag rietstrasse 4 ch-8640 rapperswil, switzerland phone: +41/55/220 9000 fax: +41/55/220 9001 austriamicrosystems uk, ltd. coliseum business centre, watchmoor park camberley, surrey, gu15 3yl, united kindom phone: +44/1276/23 3 99 fax: +44/1276/29 3 53 austriamicrosystems usa, inc. suite 116, 4030 moorpark ave, san jose, ca 95117, usa phone: +1/408/345 1790 fax: +1/408/345 1795 austriamicrosystems usa, inc. suite 400, 8601 six forks road raleigh, nc 27615, usa phone: +1/919/676 5292 fax: +1/919/676 5305 austriamicrosystems ag aios gotanda annex 5th fl., 1-7-11, higashi-gotanda, shinagawa-ku, tokyo 141-0022 japan phone: +81/3/5792 4975 fax: +81/3/5792 4976 austriamicrosystems ag suite 811, tsimshatsui centre, east wing, 66 mody road, tsim sha tsui east, kowloon, hong kong phone: +852/2268 6899 fax: +852/2268 6799 austriamicrosystems ag singapore representative office 83 clemenceau avenue #02-01 ue square singapore 239920 phone: +65 68 30 83 05 fax: +65 62 34 31 20 austriamicrosystems ag #805, dong kyung bldg., 824-19, yeok sam dong, kang nam gu, seoul korea 135-080 phone: +82/2/557 8776 fax: +82/2/569 9823 ams ag technical content still valid

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